Firstly, write barriers act as a partial orderings on store operations. Consider the following sequence of events:
|
This sequence of events is committed to the memory coherence system in an order
that the rest of the system might perceive as the unordered set of
{A=1,B=2,C=3}
all occurring before the unordered set of
{D=4,E=5}, as shown in
Figure .
Secondly, data dependency barriers act as a partial orderings on data-dependent loads. Consider the following sequence of events with initial values {B = 7, X = 9, Y = 8, C = &Y}:
|
Without intervention, CPU 2 may perceive the events on CPU 1 in some effectively random order, despite the write barrier issued by CPU 1:
In the above example, CPU 2 perceives that B is 7, despite the load of *C (which would be B) coming after the LOAD of C.
If, however, a data dependency barrier were to be placed between the load of C and the load of *C (i.e.: B) on CPU 2, again with initial values of {B = 7, X = 9, Y = 8, C = &Y}:
|
then ordering will be as intuitively expected, as shown in
Figure .
And thirdly, a read barrier acts as a partial order on loads. Consider the following sequence of events, with initial values {A = 0, B = 9}:
|
Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in some effectively random order, despite the write barrier issued by CPU 1:
If, however, a read barrier were to be placed between the load of B and the load of A on CPU 2, again with initial values of {A = 0, B = 9}:
|
then the partial ordering imposed by CPU 1's write barrier will be
perceived correctly by CPU 2, as shown in
Figure .
To illustrate this more completely, consider what could happen if the code contained a load of A either side of the read barrier, once again with the same initial values of {A = 0, B = 9}:
|
Even though the two loads of A
both occur after the load of B, they may both
come up with different values, as shown in
Figure .
Of course, it may well be that CPU 1's update to A becomes perceptible
to CPU 2 before the read barrier completes, as shown in
Figure .
The guarantee is that the second load will always come up with A == 1 if the load of B came up with B == 2. No such guarantee exists for the first load of A; that may come up with either A == 0 or A == 1.
Paul E. McKenney 2011-12-16