14.2.10.3 What May Not Be Assumed About Memory Barriers?
There are certain things that memory barriers cannot guarantee outside
of the confines of a given architecture:
- There is no guarantee that any of the memory accesses specified
before a memory barrier will be complete by the completion
of a memory barrier instruction; the barrier can be considered
to draw a line in that CPU's access queue that accesses of the
appropriate type may not cross.
- There is no guarantee that issuing a memory barrier on one CPU
will have any direct effect on another CPU or any other hardware
in the system. The indirect effect will be the order in which
the second CPU sees the effects of the first CPU's accesses occur,
but see the next point.
- There is no guarantee that a CPU will see the correct order
of effects from a second CPU's accesses, even if the second CPU
uses a memory barrier, unless the first CPU also uses a matching
memory barrier (see the subsection on "SMP Barrier Pairing").
- There is no guarantee that some intervening piece of off-the-CPU
hardware14.7 will not reorder the memory accesses. CPU cache
coherency mechanisms should propagate the indirect effects of
a memory barrier between CPUs, but might not do so in order.
Paul E. McKenney
2011-12-16