When dealing with CPU-CPU interactions, certain types of memory barrier should always be paired. A lack of appropriate pairing is almost certainly an error.
A write barrier should always be paired with a data dependency barrier or read barrier, though a general barrier would also be viable. Similarly a read barrier or a data dependency barrier should always be paired with at least an write barrier, though, again, a general barrier is viable:
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Or:
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One way or another, the read barrier must always be present, even though it might be of a weaker type.14.8
Note that the stores before the write barrier would normally be expected to match the loads after the read barrier or data dependency barrier, and vice versa:
Paul E. McKenney 2011-12-16