Pair-wise memory barriers provide conditional ordering semantics.
For example, in the following set of operations, CPU 1's access to
A does not unconditionally precede its access to B from the viewpoint
of an external logic analyzer
(see Appendix
for examples).
(the system is only to act as if the accesses
are in order; it is not necessarily required to actually
force them to be in order).
However, if CPU 2's access to B sees the result of CPU 1's access
to B, then CPU 2's access to A is guaranteed to see the result of
CPU 1's access to A.
Although some CPUs' memory barriers do in fact provide stronger,
unconditional ordering guarantees, portable code may rely only
on this weaker if-then conditional ordering guarantee.
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Quick Quiz 14.6: But if the memory barriers do not unconditionally force ordering, how the heck can a device driver reliably execute sequences of loads and stores to MMIO registers? End Quick Quiz
Of course, accesses must be either loads or stores, and these
do have different properties.
Table
shows all possible combinations of loads and stores from a pair
of CPUs.
Of course, to enforce conditional ordering, there must be
a memory barrier between each CPU's pair of operations.
Paul E. McKenney 2011-12-16