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Unfortunately, such a conclusion does not necessarily hold
on all 20th-century systems.
Suppose that the cache line containing A is initially owned
by CPU 2, and that containing B is initially owned by CPU 1.
Then, in systems that have invalidation queues and store
buffers, it is possible for the first assignments to ``pass
in the night'', so that the second assignments actually
happen first.
This strange (but quite common) effect is explained in
Appendix .
This same effect can happen in any memory-barrier pairing where each CPU's memory barrier is preceded by a store, including the ``ears to mouths'' pairing.
However, 21st-century hardware does accommodate ordering intuitions, and do permit this combination to be used safely.
Paul E. McKenney 2011-12-16