Although cache-coherence protocols guarantee that a given CPU sees its own accesses in order, and that all CPUs agree on the order of modifications to a single variable contained within a single cache line, there is no guarantee that modifications to different variables will be seen in the same order by all CPUs -- although some computer systems do make some such guarantees, portable software cannot rely on them.
To see why reordering can occur, consider the two-CPU system shown in
Figure , in which each CPU has a split
cache.
This system has the following properties:
In short, if cache A is busy, but cache B is idle, then CPU 1's stores to odd-numbered cache lines may be delayed compared to CPU 2's stores to even-numbered cache lines. In not-so-extreme cases, CPU 2 may see CPU 1's operations out of order.
Much more detail on memory ordering in hardware and software
may be found in Appendix .
Paul E. McKenney 2011-12-16