C. Why Memory Barriers?
So what possessed CPU designers to cause them to inflict memory barriers
on poor unsuspecting SMP software designers?
In short, because reordering memory references allows much better performance,
and so memory barriers are needed to force ordering in things like
synchronization primitives whose correct operation depends on ordered
memory references.
Getting a more detailed answer to this question requires a good understanding
of how CPU caches work, and especially what is required to make
caches really work well.
The following sections:
- present the structure of a cache,
- describe how cache-coherency protocols ensure that CPUs agree
on the value of each location in memory, and, finally,
- outline how store buffers and invalidate queues help
caches and cache-coherency protocols achieve high performance.
We will see that memory barriers are a necessary evil that is required
to enable good performance and scalability, an evil that stems from
the fact that CPUs are orders of magnitude faster than are both the
interconnects between them and the memory they are attempting to access.
Subsections
Paul E. McKenney
2011-12-16